Senior IP Design Verification Engineer

Technical expertise

• At least 5+ years of experience working as a Design Verification

• Solid knowledge of the ASIC/SoC development lifecycle.

• Hands-on experience with OVM/UVM methodologies using System Verilog.

• Experience in testbench development or enhancement, test case creation, coding, execution, bug investigation, regression runs, coverage analysis, and verification sign-off

• Experience with AXI VIP and AXI protocol verification.

• Hands-on experience with UCIe is highly preferred.

• Familiarity with widely used standards and protocols such as PCIe Gen3/4/5, USB3, DDR4/5, Ethernet, CSI2, I3C.

• Experience performing gate-level simulations and timing constraint simulations.

• Strong root cause analysis and debugging skills with the ability to isolate issues across testbench, integration, and IP boundaries.

• Fluent in written and spoken English.

PERSONALITY AND WORKING PRACTICE

• You thrive in a dynamic and fast-paced work environment, embracing challenges and change.

• You work proactively, self-organized and you are keenly interested in taking over responsibility.

• You are highly collaborative and eager to contribute to team success, with a strong willingness to continuously learn and improve.

• Your "out-of-the-box thinking" helps to achieve creative and effective solutions to complex problems.

• You exhibit a hands-on mentality, eager to delve into technical details and provide direct support to developers and team members.

• You are highly motivated in tailoring and optimizing processes to enhance efficiency and overall project outcomes.

EDUCATION

• Bachelor’s degree in Electronics, Electrical Engineering, or a comparable discipline.